Question about peephole2 and addressing mode

[Jeff Law]

On 01/22/10 06:23, Mohamed Shafi wrote:
> 2010/1/22 Richard Henderson<rth@redhat.com>:
>    
>> On 01/21/2010 06:22 AM, Mohamed Shafi wrote:
>>      
>>> Hello all,
>>>
>>> I am doing a port for a 32bit a target in GCC 4.4.0. The target
>>> supports (base + offset) addressing mode for QImode store instructions
>>> but not for QImode load instructions. GCC doesn't take the middle
>>> path. It either supports an addressing mode completely and doesn't
>>> support at all. I tried lot of hacks to support  (base + offset)
>>> addressing mode only for QI mode store instructions. After a lot of
>>> fight i finally gave up and removed the QImode support for this
>>> addressing mode completely in GO_IF_ LEGITIMATE_ADDRESS macro. Now i
>>> am pursing an alternate solution. Have peephole2 patterns to implement
>>> QImode (base+offset) addressing mode for store instructions. How does
>>> it sound?
>>>        
>> It doesn't sound totally implausible.  But as you notice, peepholes only act
>> on sequential instructions.  In order to assist generating sequential
>> instructions, you could try allowing base+offset in non-strict mode.
>>
>> I fear you'll likely have to use a combination of methods in order to get
>> decent code here.
>>      
>   can you point out the combination of the methods in your mind? And by
> the way is it possible to allow the addressing mode completely and
> then break it down into register indirect addressing mode after reload
> pass?
>    
I would recommend you look at how the PA port handles these problems.  
It has integer indexed loads, but no stores.  You have to reject these 
addresses in GO_IF_LEGITIMATE_ADDRESS, but you can make operand 
predicates & constraints which allow these addressing modes.

Jeff