BImode is treated as normal byte-wide mode and causes bug.

Bingfeng Mei
Fri Dec 10 09:59:00 GMT 2010

I am investigating a bug in our target port. It is
due to following optimization done by combine pass. 

(zero_extend:SI (reg:BI 120))

is transformed to 

(and:SI (subreg:SI (reg:BI 120) 0)
    (const_int 255 [0xff]))

in expand_compound_operation (combine.c), where BImode is 
just treated as a byte-wide mode.

In machmode.def, BImode is defined as FRACTIONAL_INT_MODE (BI, 1, 1).
But the precision field is not used at all here. 

Even after I hacked the code to bypass the transformation. 

(subreg:QI (zero_extend:SI (reg:BI 120)) 0)

is still transformed to 
(subreg:QI (reg:BI 120) 0))

in simplify_subreg. This is wrong because the higher bits
of paradoxical subreg is undefined here, not zeros.

Grep GET_MODE_PRECISION returns not many results. It seems
that many rtx optimization functions don't consider 
FRACTIONAL_INT_MODE at all. If that is the case, we should
document that limitations (or maybe I missed it).

We need zero_extend BImode to model behaviour of moving 
lowest bit of predicate register into general register. 


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