combine two load insns

[Jeff Law]

On 12/08/10 09:18, Frederic Riss wrote:
>
> OK, I see your point, but I tend to think the the odds of the register
> allocator being able to coalesce the additional DI->SI moves in the
> pre-IRA approach are by far higher that the odds of having merge
> candidates after register allocation.
I agree, but note that failure to coalesce leads to code quality regression.

Also note that handling of double-word values is, IMHO, the allocator's 
biggest problem area.  This has been greatly helped by Bernd's recent 
work, but there's still significant amounts of work to do here.


>   I agree with your suggestion of
> being able to do that in the scheduler though, it might be a good fit,
> even if it's not a scheduling issue in the first place.
It may not be a scheduling issue, but it's been known for 20 years that 
GCC's scheduler has the necessary bits to do these kinds of memory 
optimizations.   We've just never taken the time to utilize the 
dependency information available in the scheduler in any way other than 
to reorder insns to improve pipeline behavior.   One could even argue 
that the dependency info in the scheduler should be pushed out to other 
passes that could easily make use of such information.

Jeff