combine two load insns

Jeff Law
Tue Dec 7 13:18:00 GMT 2010

On 12/06/10 15:07, Ian Lance Taylor wrote:
> roy rosen<>  writes:
>> If I have two load SI insns. Is there any way to combine them into one
>> load DI insn?
>> Not using peephole which can catch only this limited case of being
>> sequential insns.
>> I have seen something done in ARM (*arith_adjacentmem) but it is very
>> awkward and would not be realistic if the DI is being used by many
>> different intrinsics.
> As far as I know there is no general pass which does this at present.
> So it would currently have to a combine pattern like arith_adjacentmem,
> or a peephole, or a machine specific pass.
> On many processors the alignment requirements of DImode and SImode loads
> are different, so it would be hard to do this as a fully general pass.
Given the two loads don't have a def-use data dependency combine won't 
ever get the opportunity to do anything with them.  In general there is 
no pass which combines insns without a true data dependency and targets 
which have such insns have had to handle those combinations in machine 
dependent reorg.  In fact, it was the combination of independent insns 
which led to the introduction of the machine dependent reorg pass eons ago.

I've speculated that this kind of optimization could be done in the 
scheduler.  The basic idea is to first realize that the memory 
references can be combine if they can be issued at the same time 
otherwise there's some kind of dependency that gets in the way.  So the 
thing to do is see if an insn moving to the ready queue can be combined 
with other insns already in the ready queue.

Of course you'd need the machine checks to verify the combination, but 
that wouldn't be terribly hard to handle.


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