How to split 40bit data types load/store?

[Richard Henderson]

On 09/14/2009 07:24 AM, Mohamed Shafi wrote:
> Hello all,
>
> I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
> 40bit data (_Accum) in the port. The target has 40bit registers which
> is a GPR and works as 32bit reg in other modes. The load and store for
> _Accum happens in two step. The lower 32bit in one instruction and the
> upper 8bit in the next instruction. I want to split the instruction
> after reload. I tired to have a pattern (for load) like this:
>
> (define_insn "fn_load_ext_sa"
>   [(set (unspec:SA [(match_operand:DA 0 "register_operand" "")]
> 	            UNSPEC_FN_EXT)
>         (match_operand:SA 1 "memory_operand" ""))]
>
> (define_insn "fn_load_sa"
>   [(set (unspec:SA [(match_operand:DA 0 "register_operand" "")]
>                      UNSPEC_FN)
>         (match_operand:SA 1 "memory_operand" ""))]

Unspec on the left-hand-side isn't something that's supposed to happen, 
and is more than likely the cause of your problems.  Try moving the 
unspec to the right-hand-side like:

   (set (reg:SI reg) (mem:SI addr))

   (set (reg:SA reg)
        (unspec:SA [(reg:SI reg) (mem:QI addr)]
                   UNSPEC_ACCUM_INSERT))

and

   (set (mem:SI addr) (reg:SI reg))

   (set (mem:QI addr)
        (unspec:QI [(reg:SA reg)]
                   UNSPEC_ACCUM_EXTRACT))

Note that after reload it's perfectly acceptable for a hard register to 
appear with the different SI and SAmodes.

It's probably not too hard to define this with zero_extract sequences 
instead of unspecs, but given that these only appear after reload, it 
may not be worth the effort.


r~