worst case register classes (Was: Re: IRA_COVER_CLASSES for m32c)

[Joern Rennecke]

As I've said before, m32c is probably a "worst case" scenario for gcc
as it has not one, not two, not even three, but FOUR different types
of registers (8/16 bit general, 16 bit only general, 24 bit address
registers, and control (incl $fp) registers), and only a small number
(2) of each.

I think our mxp is more 'interesting'.  It got several hundred register
classes, auto-generated, and some important ones have only a single member.

We got a number of vector registers, a flags register, and an accumulator.
All of them are 128 bit wide and an 8-bit mask selects which 16-bit wide
lanes of the 128 bit word are operated on - i.e. 255 different combinations.
A lot of instructions clobber the accumulator and/or the flags
and to make sure that the registers are lined up, I have to make flags and
accumulator allocated registers.
Then the first few of the vector registers are also special because they
can also be used as 16 and 32 bit scalar registers.
A truely complete register class set would have 2^32 register classes even
before getting into such niceties as call used / clobered regs and sibcalls,
but I considered this slightly impractical considering the amount of
memory that would cost.