Pipeline hazards and delay slots

[Mohamed Shafi]

Hello all,

In the gcc port that i am currently working on delay slots are getting
filled with instructions that require a nop between them.
Say,

call fun
lw R0, R8
add R1, R0

This is an example where both the delay slots have been filled.
But 'add' instruction has a true data dependency on 'lw' instructions
and require a delay of one cycle between them. Noramlly this is done
by inserting a nop between such instructions if instruction scheduler
doesn't schedule instructions properly. Currently i am doing this in
final_prescan just like in MorphoRISC1 (mt).
But how can i handle instances like this? Should i be doing insertion
of nops in reorg pass?

Thanks for your time.

Regards,
Shafi