GCC : how to add VFPU to PSP Allegrex (MIPS target) ?

[Jim Wilson]

Christophe Avoinne wrote:
>    * How can I make coexist the SF mode between the FPU registers and
>      the VFPU registers in the argument list of a function ? 

You probably don't want to use VFPU registers for argument passing. 
That will complicate the ABI.  If you really do, then you need two 
different "float" types, which in turn may cause other problems.

>    * Another way to distinguish a VFPU scalar is to use "typedef  float
>      __attribute__((vector_size(4))) V1SF;". Is that difficult to make
>      it possible (right now, gcc refuses it) ?

See the code in make_vector_modes in genmodes.c.
       /* Do not construct vector modes with only one element, or 

          vector modes where the element size doesn't divide the full 

          size evenly.  */
That is only the first step though.  I'm not sure what the rest of gcc 
will do for single element vectors.

>    * Same question for V3SF, is that difficult to make it possible ?

Not obvious what the problem is here, seems like it should already be 
possible to do this.

>      first 32 registers, would it be difficult to have combined V2V1SF,
>      V3V1SF, V4V1SF to define column vectors of two, three or four
>      components ? and to have V2V2SF, V3V3SF, V4V4SF as matrixes ?

The gcc support was designed to handle SIMD instructions.  There is some 
support for stride on memory accesses, but not within the register set. 
  I don't think there is any way to support column or matrix vectors at 
this time.

You might get better responses if you put something obvious like 
"autovectorization" in the subject line.  The people doing this work 
might not have realized that this message was relevant to them.

Jim