atomic accesses

[Paul Brook]

> AFAIK the only reason we don't break this rule is that doing so would
> be grossly inefficient; there's nothing to stop any gcc back-end with
> (say) seriously slow DImode writes from using two SImode writes instead.

I'm fairly sure ARM already breaks this "rule".

Currently it probably only effects postincrement addressing modes.  However 
there is definite scope for splitting loads/stores (even SI->2*HI) when 
optimizing for size.

Paul