Hi,
I am working on porting GCC to a new RISC architecture. The ISA does not
have a "Jump and Link Register" instruction. So I am simulating one by
replacing
jal [reg]
by
load ra, Lret
jr reg
Lret:
in RTL.
But my return label is getting optimized away. Could you please tell me
how to avoid this.
Also, is this the correct approach.
Thanks in advance,
Kunal