About Loop Pattern ----GCC porting

[redriver jiang]

Hello:
       I am Jiang Hongjiang and recently I am porting the GCC backend
to a DSP, and get puzzled about the "decrement_and_branch_until_zero"
pattern.By Reading the GCC source, I find that this pattern is used in
loop optimization, and it's used under the condition of defining the
"doloop_end" pattern. Inspired by the c4x machine description file(
c4x.md), I defined the "doloop_end" pattern using "define_expand", and
generate the "decrement_and_branch_until_zero" insn in the preparation
statements. Right now the GCC can generate the
"decrement_and_branch_until_zero" insns and its related assemble
insn(in my platform it is "DJNZ Rn,lable"), but I find that the GCC
remains other insns(the cmp insns and other) unchanged. How do you
delete the "CMP" insn and other insn in the loop while using the
"decrement_and_branch_until_zero" pattern? The accessory demonstrates
a example.


Thanks!
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Given the C code:
              int i;
	      for(i = 0 ; i < 5; i++)
		;
the C4x generates assemble insn as follows:
	lda 4,ar0
  L2:
    	dbu ar0,L2

and in my platform, it generates such assemble:
	LDRI, R11,0
        LDRI  R10,5
   L2:
	ADDI  R11,1
	CMP   R11,5
	DJNZ  R10,L2
   The first two insn load immediate operand 0 and operand 5 into Reg R11 and R10, the " ADDI R11,1" insn 
adds R11 by 1, the "CMP R11,5" insn compares R11 between 5. 

    If I don't define "doloop_end" pattern, it generate such assemble:
	LDRI, R11,0
   L2:
	ADDI  R11,1
	CMP   R11,5
	BNE   L2

   Obviously the "decrement_and_branch_until_zero" replace the "BNE L2" and remains the "ADDI R11,1" and " CMP R11,5"
unchanged.