vliw scheduling - TImode bug?

[Hariharan Sandanagobalane]

Hello,
I see quite a few instances when i get the following RTL. A conditional 
branch, followed by a BASIC_BLOCK note, followed by a non-TImode 
instruction. Theoretically, i should be allowed to package the non-TI 
instruction along with the conditional branch, but doing so seems to be 
produce incorrect results. Am i supposed to consider the 
NOTE_INSN_BASIC_BLOCK as a cycle-breaker? Or, is it a genuine bug in the 
way TImodes are set on instructions?

(jump_insn:TI 144 225 17 2 
/home/hariharans5/gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/931004-8.c:15 
(parallel [
            (set (pc)
                (if_then_else (le:HI (reg:CC 17 pseudoCC)
                        (const_int 0 [0x0]))
                    (label_ref 109)
                    (pc)))
            (use (const_int 77 [0x4d]))
        ]) 10 {*branch} (nil)
    (expr_list:REG_DEAD (reg:CC 17 pseudoCC)
        (expr_list:REG_BR_PROB (const_int 500 [0x1f4])
            (nil))))

(note 17 144 124 3 [bb 3] NOTE_INSN_BASIC_BLOCK)

(note 124 17 21 3 
("/home/hariharans5/gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/931004-8.c") 
17)

(insn 21 124 196 3 
/home/hariharans5/gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/931004-8.c:15 
(set (reg:HI 3 R3)
        (plus:HI (reg/f:HI 13 FP)
            (const_int 12 [0xc]))) 31 {*lea_move} (nil)
    (nil))

Thanks and regards
Hari