VLIW scheduling and delayed branch

[Pranav Bhandarkar]

On Dec 9, 2007 2:19 AM, Thomas Sailer <sailer@ife.ee.ethz.ch> wrote:
> > Has anyone faced a similar problem before? Are there targets for which
> > both VLIW and DBR are enabled? Perhaps ia64?
>

Ok, this was a long time back, but Yes I have faced a similar problem.
We disabled
delayed branch scheduling and used the machdep reorg pass. We examined
the dependencies of the
branch instructions moving backwards from the branch instruction and
marking all the instructions ( and the
containing insn bundle) that the branch depended upon. Then again,
moving backwards from the branch
insn, we picked the first insn bundle with all unmarked insns ( and
cycle size of the bundle <= no of delay slots
of a branch insn ) and put that bundle into the delay slot.

This approach worked fine for the small testcases that we had, but we
really didnt test this on any monstrous piece of software. We
implemented this for the TMS320C6x VLIW DSP.

HTH,
Pranav