volatile and R/M/W operations

[Robert Dewar]

Richard Kenner wrote:
>>> 	t1 = y | 2;
>>> 	y = t1;
>>>
>>> are very hard to tell apart at the RTL level.  Though it's clear that
>>> a single instruction might best match the expect semantics of the former,
>>> it's a lot less clear that it would for the latter.
>> I think it would still be OK for the latter, why not?
> 
> There was certainly a time when it would not, because a R/M/W cycle on
> a device register meant a different thing that a read followed by a write
> and the latter is more clearly what the above is supposed to represent.
> 
> Whether there is still such hardware around is another question, but
> the point is that whether you or I THINK it would be OK really isn't
> the issue when talking about legacy code.

What is interesting is whether this translation is appropriate for
modern Intel architecture chips, and as far as I know the answer
is yes.