paired register loads and stores

[Erich Plondke]

On 9/29/06, David Edelsohn <dje@watson.ibm.com> wrote:
> >>>>> Erich Plondke writes:
>
> Erich> rs6000 and Sparc ports seem to use a peephole2 to get the ldd or lfq
> Erich> instructions (respectively), but it looks like there's no reason for
> Erich> the register allocater to allocate registers together.  The peephole2
> Erich> just picks up loads to adjacent memory locations if the allocater
> Erich> happens to choose adjacent registers (is that correct?) or the
> Erich> variables are specified as living in hard registers with the help
> Erich> of an asm.
>
>         On both rs6000 and sparc, the code includes a test that the
> registers are adjacent.  See registers_ok_for_quad_peep() in rs6000.md and
> rs6000.c, and equivalent in sparc.

Yes, but peephole2 lives after register allocation, so how does the target
tell the register allocator that adjacent values loaded from memory should
also attempt to be placed adjacent in the register file?

It looks like if they /happen/ to be allocated together in the
register file, the
peephole pattern will catch them, but I don't see anything to help them be
allocated in such a way.

-- 
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