Modifying ARM code generator for elimination of 8bit writes - need help

[Daniel Jacobowitz]

On Tue, May 30, 2006 at 09:03:54PM +0100, Paul Brook wrote:
> > I found arm.md and the moveqi insns, but because of the different
> > addressing modes of strb and swpb, its not easy to make the change.
> > And there must be a compiler option for this, too.
> >
> > Could somebody please tell me how to implement this change?
> 
> Short answer is probably not.
> 
> There are a couple of complications that spring to mind. The different 
> addressing modes and the fact that swp clobbers a register are the most 
> immediate ones.
> 
> You'll need to modify at least the movqi insn patterns, memory constraints and 
> the legitimate address stuff. I'm not sure about the clobber, that might need 
> additional reload-related machinery.

I suspect it would be better to make GCC do halfword stores instead
(read/modify/write).

-- 
Daniel Jacobowitz
CodeSourcery