address order and BB numbering

[sean yang]

>From: Dale Johannesen <dalej@apple.com>
>To: sean yang <seanatpurdue@hotmail.com>
>CC: Dale Johannesen <dalej@apple.com>, gcc@gcc.gnu.org
>Subject: Re: address order and BB numbering
>Date: Fri, 19 May 2006 12:54:56 -0700
>
>
>On May 19, 2006, at 12:48 PM, sean yang wrote:
>
>>Although "BASIC_BLOCK array contains BBs in an unspecified order"  as the 
>>GCC internal doc says, can I assume that the final virtual  address for an 
>>instruction in BB_m is always higher than the  virtual address for an 
>>instruction in BB_n, when m < n.  (Let's  assume the linker for the target 
>>machine produce code from low  address to high address.)
>
>Definitely not.
>Various phases that need to know the order of insns produce a CUID  for 
>that phase, but it is not maintained globally.

Thanks for the answer.
Then this must be a very dummy question.  How the compiler keep the 
instruction order in the RTL IR format in a function? By the information 
like "insn 50 56 51" ? e.g.,
(insn 50 56 51 4 (clobber (reg/i:SI 0 ax)) -1 (nil) )



>

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