GNU C++ 4.0.1/4.1.0 cache misses on MICO sources.

[Karel Gardas]

On Tue, 17 May 2005, Andi Kleen wrote:

> Karel Gardas <kgardas@objectsecurity.com> writes:
>
>> I've thought that L1 and L2 DTLB misses are the most important for the
>> overall performance or performance degradation, if not please correct
>> me since this is my first attempt to measure and interpret such data.
>
> TLB is just for caching the translations from virtual to physical
> addresses. Normally the data/instruction cache misses are more
> important. There are a few TLB intensive workloads too, but they tend
> to use much more memory than gcc normally does.

Thanks for TLB explanation!

> So I think you should rather use ICACHE_MISSES and DATA_CACHE_REFILLS_FROM_SYSTEM,
> which measure the "real" L2 caches.

OK, will do, although I'm not so sure ICACHE_MISSES means L2 I cache, 
since DCACHE_MISSES in case of D cache seems to means L1 cache, am I 
right?

> And perhaps run a normal instruction profile (CPU_CLK_UNHALTED) in parallel and
> double check the hot spots displayed by the others match the real
> time hogs. Note you can use upto three performance counters at the same time.

CPU_CLK_UNHALTED was provided in my previous email and the results were 
povided on its basis, i.e. table sorted by CPU_CLK_UNHALTED column. IIRC 
oprofile also warned me that maximum number of perf. counters in used is 
four -- that was after the attempt to throw all cache misses into 
measurement. :-)

Thanks for your corrections/ideas!
Karel
--
Karel Gardas                  kgardas@objectsecurity.com
ObjectSecurity Ltd.           http://www.objectsecurity.com