Problem with Delayed Branch Scheduling

[Steven Bosscher]

On Monday 04 July 2005 12:41, Balaji S wrote:
> _On 04-Jul-2005 15:31, Steven Bosscher san wrote_:
> > Add an attribute to those instructions that cannot be in delay slots,
> > and change this define_delay to disallow instructions with that attr?
>
> Any instruction other than jump can be placed in the delay slot. I hope
> "!jump" can fulfill this requirement.
>
> I don't have any idea to identify a part of a VLIW instruction and disallow
> it delay slot. I only know that TImode of insn signifies a new cycle start.
> please hlep me by giving some pointers.

Ah, I think I misunderstood your problem.

So you have a few instructions bundled into a VLIW instruction, and
one of the instructions in the bundle is moved into the delay slot,
thus breaking your VLIW bundle.  Right?

That is a much harder problem...  I don't think it is really possible
with the existing dbr scheduling pass, but maybe someone else knows a
trick for this...

Gr.
Steven