Question about instruction packing

[Balaji S]

_On 03-Jan-2005 13:24, Steven Bosscher san wrote_:
> On Monday 03 January 2005 07:47, Balaji S wrote:
> 
>>Hi all,
>>
>>I am working on a DSP processor which can issue two instructions, each one
>>word, in one cycle.
>>
>>The following is the DFA description for the above behavior.
>>
>>(define_automaton "ic3")
>>(define_cpu_unit "ic3_slot0, ic3_slot1" "ic3")
>>
>>(define_insn_reservation "ic3_any" 1
>>  (eq_attr "length" "1")
>>  "ic3_slot0|ic3_slot1")
>>
>>(define_insn_reservation "ic3_all" 1
>>  (eq_attr "length" "2")
>>  "ic3_slot0+ic3_slot1")
>>
>>With the above descriptions the instructions are getting rearranged but the
>>packing info, *TImode for insn*, is not available. Please correct me if any
>>mistakes in descriptions and guide me to get the packing info in insns.
> 
> 
> Looks very similar to m32r.  Look at the DFA description for
> that target, maybe there's something useful to learn for you
> there.
> 
Thanks for your pointer.

Had a look in to your patch.

> 2004-06-28  Steven Bosscher  <stevenb@suse.de>
> 
> * config/m32r/m32r.c (m32r_sched_odd_word_p, m32r_adjust_cost,
> m32r_sched_init, m32r_sched_reorder, m32r_variable_issue): Remove.
> (TARGET_SCHED_ADJUST_COST, TARGET_SCHED_VARIABLE_ISSUE,
> TARGET_SCHED_INIT, TARGET_SCHED_REORDER): Don't define.
> * config/m32r/m32r.md: Rewrite the pipeline description as a DFA.

Found that, missing scheduling related target definition (TARGET_SCHED_ISSUE_RATE) created that problem.

After solving that, now i have a different problem with packing that two insns of two word each are getting packed together. Do i need to control this using TARGET_SCHED_VARIABLE_ISSUE?. If not, please guide me to specify this in DFA description itself.