Question about instruction packing

[Balaji S]

Hi all,

I am working on a DSP processor which can issue two instructions, each one word, in one cycle.

The following is the DFA description for the above behavior.

(define_automaton "ic3")
(define_cpu_unit "ic3_slot0, ic3_slot1" "ic3")

(define_insn_reservation "ic3_any" 1
  (eq_attr "length" "1")
  "ic3_slot0|ic3_slot1")

(define_insn_reservation "ic3_all" 1
  (eq_attr "length" "2")
  "ic3_slot0+ic3_slot1")

With the above descriptions the instructions are getting rearranged but the packing info, *TImode for insn*, is not available. Please correct me if any mistakes in descriptions and guide me to get the packing info in insns.

Thanks in advance.

Balaji Sivan