Store scheduling with DFA scheduler

[Jon Beniston]

Hi,

I'm trying to get the DFA scheduler in GCC 4.0.0 to schedule loads and
stores, but I can only get it to work for loads. I have an automaton defined
as follows:

(define_automaton "cpu")

(define_cpu_unit "x" "cpu")
(define_cpu_unit "m" "cpu")

(define_insn_reservation "arith" 1 (eq_attr "type" "arith") "x")
(define_insn_reservation "loads" 2 (eq_attr "type" "load") "x,m")
(define_insn_reservation "stores" 3 (eq_attr "type" "store") "x,m*2")

All instructions take one cycle in "x". Loads then take one "m" cycle, while
stores take two "m" cycles. Basically stores aren't fully pipelined.

If I compile the following code:

int x, y, z, w;
void main()
{
 x = x + 1;
 y = y + 1;
 z = z + 1;
 w = w + 1;
}

I get the following output:

 lhu      r4, [x]
 lhu      r5, [y]
 lhu      r6, [z]
 lhu      r7, [w]
 add      r4, 1  
 add      r5, 1  
 add      r6, 1  
 add      r7, 1  
 sh       [x], r4
 sh       [y], r5
 sh       [z], r6
 sh       [w], r7

This therefore seems to be scheduling loads correctly, as before I added the
automaton I was getting adds immediately following loads, but doesn't seem
to be scheduling the stores correctly, as they are scheduledin consequtive
slots. I would expect the optimial schedule to be something along the lines
of:

 lhu      r4, [x]
 lhu      r5, [y]
 lhu      r6, [z]
 lhu      r7, [w]
 add      r4, 1  
 sh       [x], r4 
 add      r5, 1  
 sh       [y], r5
 add      r6, 1  
 sh       [z], r6
 add      r7, 1  
 sh       [w], r7

I'd be greatful for any suggestions as to what the problem might be.

Cheers,
Jon