Interesting paper from Perdue

[tm_gccmail@kloo.net]

On Mon, 20 Sep 2004, Steven Bosscher wrote:

> I don't know if anyone has ever seen/read/mentioned this paper
> before, I might have missed it.  Otherwise, interesting reading:
> https://engineering.purdue.edu/ECE/Research/TR/2004pdfs/TR-ECE-04-01.pdf
> 
> Gr.
> Steven

I'll digress and rant a bit; apologizes in advance.

This is just the tip of the iceberg, really. There are many other 
instances where various optimizations are improved in isolation and 
degrade performance because they don't consider the effects on the other
optimization passes.

For example, Some of the recent work on alias analysis really worries me
because I believe this will result in a medium-term net performance
decrease on many targets.

Consider:

1. Improved alias analysis allows better disambiguation of memory 
   references.

2. The current scheduler is overly aggressive about hoisting loads, and
   is only restrained by the inadequacy of the current alias analysis.

   When alias analysis is improved, the first scheduling pass will
   greatly increase register pressure.

3. The register allocator inserts code suboptimially (in particular,
   restores are too early) and lacks basic fatures such as live-range
   splitting and rematerialization.

   Therefore, it exhibits increasingly bad behavior as register pressure
   increases.

I think the following will occur:

1. Targets with the first instruction scheduling pass enabled will exhibit
   a net decrease in performance due to increased register pressure. This
   will be exacerbated if the target has fewer registers (e.g. slightly
   worse on IA64, much worse on PPC). The SH is unlikely to be affected
   due to scheduler modifications already implemented.

1. Targets without the first scheduling pass enabled will exhibit a net
   decrease in performance only if the register set is very small
   (fewer than 16 registers). This includes the x86 and most embedded
   processors such as the H8/300, M68HC11, 8051, etc.

As I see it, the register allocator and the instruction scheduler are
really the base of the foundations for GCC optimization.

We keep adding improvements which:

1. Allow more intermediate values to be kept in registers which increase
   register pressure

2. Allow memory to be retained in registers longer, which increases
   register pressure

3. Create larger basic blocks, which increases register pressure

4. Allow more loop unrolling, which increases register pressure

5. etc

...and the register allocator doesn't handle the increased register
pressure well, so the net result is very little improvement.

We really spend some time improving the foundation of GCC instead of
piling more and more optimizations on top of it.

Toshi