More on memory barriers

[Richard Henderson]

On Wed, Sep 15, 2004 at 05:25:48PM -0400, Jason Merrill wrote:
> I understand why the memory barrier is needed, my question had to do with
> why it would need to look like
> 
> MB
> if (test)
>   initialize
> 
> rather than
> 
> if (test)
>   initialize
> else
>   MB
> 
> since "initialize" already contains a MB in the form of a mutex lock.

Hmm.  So the failure scenario is "data" is in cache, and out of
date, and "test" is not in cache.  Load from test pulls in the
new cacheline, sees that we skip initialize.  

You're correct, a MB there on the else path flushes "data" from
cache such that the following reference pulls in the new value.

> The Itanium ABI manual that documents the __sync intrinsics distinguishes
> between acquire barriers (disallow movement from after the barrier to
> before it), release barriers (disallow movement from before the barrier to
> after it), and full barriers (disallow all movement of memory references
> across the barrier).

This is a looser description than I find for the actual instructions.


r~