question about scheduling optimization in machine description

[Spundun Bhatt]

Hi all..

I have a couple of problems with my target which I have been ffighting 
with for a few months now, so I have decided to try here. In this email 
I am writing about on of them. It will be great if someone can suggest a 
way out of it.. if not.. a pointer to a simlar implementation in any of 
the existing target would be great.

On my architecture, floating point instructions run faster when put 
backto back with no integer or load/store instructions in the middle.  
So I want to ask the compiler to group as many such instructions 
togather as possible. The reason is that FP unit is pipelined and it 
stalls all instructions except other floating point instructions until 
the float pipeline is clear. (to save on WB hazard detection). 

I have thought about this a lot but ccant find a solution that will be 
helpful... any ideas? or has it been done for some target for certain 
instructions?

Thanx
Spundun

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