IA64 floating point division question

[Zack Weinberg]

Steve Ellcey <sje@cup.hp.com> writes:

>> I'm fairly sure that your problem is with the "*recip_approx"
>> instruction, which is what is supposed to match this pattern.  The
>> catch is, it *only* allows XFmode operands, whereas you're trying to
>> feed it SFmode.
>
> No, I created some new versions of *recip_approx that "generate" SFmode
> or DFmode (as well as some new _alts instructions) so that I can refer
> to each register in only one mode. My new *recip_approx_sf instruction
> is:
>
> (define_insn "*recip_approx_sf"
>   [(set (match_operand:SF 0 "fr_register_operand" "=f")
>         (div:SF (const_int 1)
>                 (match_operand:SF 3 "fr_register_operand" "f")))
>    (set (match_operand:BI 1 "register_operand" "=c")
>         (unspec:BI [(match_operand:SF 2 "fr_register_operand" "f")
>                     (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
>    (use (match_operand:SI 4 "const_int_operand" ""))]
>   ""
>   "frcpa.s%4 %0, %1 = %2, %3"
>   [(set_attr "itanium_class" "fmisc")
>    (set_attr "predicable" "no")])

Odd; that certainly ought to match the pattern you showed.  I have no
idea why it wouldn't.

zw