VLIW pack and DFA scheduler:Register sharing question

[mike@csdn.sign.idv.tw]

Hello,
    I have a question of registers shared by two vliw cpu function
    units.
    
    -----------------
    |   Register    |
    |    File       |
    -----------------
       |        |
    ------    ------
    |RISC|    |RISC|
    |UNIT|    |UNIT|
    ------    ------

    This two RISC units could execute instruction parallelly.

    Here is my question: Could the DFA scheduler prevents the
    following situitaion?

    add %r1,$24
    add %r1,$28

    If the two asm instruction execute parallelly, the result
    of r1 could not be known.

    Could DFA scheduler automatically prevent this situiation?

    OR I have to add some codes to prevent this?

    Please help. Thanks very much.


Mike Wu