Letter to DDJ

[Andrew Pinski]

On May 5, 2004, at 04:00, Andi Kleen wrote:

> Laurent GUERBY <laurent@guerby.net> writes:
>
>> I believe you need to add a special instruction
>> to prevent the hardware to reorder the execution of rdtsc
>
> The P4 wont, but AMD CPUs will (especially K8).
>
>> leading to wrong measurement, I don't remember what it was
>> and the GCC asm for it though, may be someone else can help...
>
> Before the RDTSC:
>
> int tmp;
> asm volatile("cpuid" : "=a" (tmp) : "0" (1) : 
> "ebx","ecx","edx","memory")

Well that will not work on some targets where the PIC register is ebx.

   __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
            : "=a" (fl1) : "0" (0) : "edx", "cc");

That will work on ever x86 target.

See gcc/testsuite/gcc.dg/i386-cpuid.h for more information.

Thanks,
Andrew Pinski