Disqualifying instructions for branch delay slot scheduling

[Barry Wealand]

Hello -

We're working with a custom MIPS-like architecture, and have discovered
a few bugs in our hardware design.  One way that we can work around
these bugs is to modify our GCC toolchain so that it places NOPs after
or before a small number of specific instructions.  The approach of
favor seems to be to modify the assembler to change these specific
instructions into two-instruction macros, with the NOP placed before or
after as appropriate.  In order for this to be completely effective,
however, we also need to be sure that the compiler never places these
instructions into branch (or jump, or call) delay slots.

Can anybody quickly summarize how one would go about disqualifying
certain specific instructions for branch delay slot scheduling?  Any
guidance at all would be greatly appreciated.

Barry Wealand
barry.wealand@lmco.com