Help with writing RTL for RISC CPU

[Richard Henderson]

On Thu, Mar 04, 2004 at 10:51:50PM +0000, David Addison wrote:
>            srl8,byte   %0, %1, %0
[...]
> The srl8,byte instruction shifts the loaded DI register appropriately 
> based on the alignment of the address in %1. Here %1 must be a single 
> register.

You should probably copy non-BWX alpha, since our "extbl" instruction
probably matches up well with your "srl8,byte".


r~