IA64 GCC bootstrap problem

[Steve Ellcey]

> I have created a (very) small example of where GCC is going wrong in the
> IA64 bootstrap though I am not sure what to do with it.

Well, ignore my earlier rambing about changing allocno_compare to deal
with fuzzy math.  It turns out there is a real bug in the inline code
for double precision floating point division.  The minimum latency
version is OK but the maximum throughput version is wrong.  I have a fix
that I am testing on a bootstrap but it does make my small test case get
the right answer.

I'll send a patch when I have tested it but if you look at
divdf3_internal_thr in ia64.md, the 3rd mult from the end is setting
operand 9 and it uses operands 7 and 3 as inputs when it should be using
operands 7 and 6 according to the example from the IA-64 manual.

Steve Ellcey
sje@cup.hp.com