Does any one have the idea how the gcc FR-V port solves this kind of problem ?

[Hsin-Hsien Wu]

Hello,
 
Recently, I am porting an experimental CPU to gcc. The cpu is much like the
FR-V CPU. It is a vliw cpu.
Here is my problem: I am trying to solve the register allocation problem.
The problem may occur in the following
situation: (Assume: A RISC FU has a five stage pipeline. Each stage need one
cycle.)
 
The experimental CPU contains more than one RISC Function Unit which shares
the REGISTER FILE.
 
 
problem #1 (Data Hazard)
ADD.p   r1 , r2 , r3          // RISC FU 1    r1 <--r2 + r3  
ADD      r1 , r4 , r5          // RISC FU 2    r1 <--r4 + r5
".p" means that the following asm instruction is executed parallelly.   This
causes the value of r1 is unpredictable.
 
problem #2 (Data Hazard)
If the RISC FU 2  needs the result value calculated by the RISC FU 1, the
RISC FU 2 has to wait the RISC FU1 to finish its cycles.
 
1  ADD.p   r1 , r2 , r3          // RISC FU 1    r1 <--r2 + r3  
2  ADD      r4 , r5 , r6          // RISC FU 2    r4 <--r5 + r6
3  ADD.p   r3 , r2 , r1          // RISC FU 1    r3 <--r2 + r1          
4  ADD      r1 , r4 , r5          // RISC FU 2    r1 <--r4 + r5

 
3 --- The problem occurs.  The value of r1 is unpredictable since RISC FU 1
doesn't finish the stage of writing the value back to register r1.
4 --- The problem occurs.  The value of r1, r4 is unpredictable since RISC
FU 1, RISC FU 2 doesn't finish the stage of writing the value back to
register r1,r4. 
This is a data hazard.  
I have taken a look at the FR-V CPU spec , and the FR-V also shares the
register file between the Integer Unit.
Does any one have the idea how the gcc FR-V port solves this kind of problem
?
 
Thanks.
 
Mike