ARM condition code register handling

[Ian Lance Taylor]

Richard Earnshaw <rearnsha@arm.com> writes:

> I've just tried this patch on the CSiBE benchmark, although it is a slight 
> win, the detailed results are much less conclusive -- some files are not 
> inconsiderably larger when this patch is used.
> 
> 	Before		After		Delta
> O2	1201677		1201305		-0.03%
> Os	1153205		1152741		-0.04%
> 
> But on some individual files we have:
> 
> bzip2/bzip2 -Os		12884	12936	+0.4%
> osdemo/gltestperf -Os	6432	6478	+0.68%
> 
> It would be good to establish why some of these tests are now worse, it 
> might be that by disabling the early CSE of these values we can make 
> things worse as well.

I see why this is happening, and I see how to fix it.

But I also tried this test case on the tree-ssa branch with no
modifications, and the results were nearly as good.  The optimizations
were all done at the tree level before generating RTL.  So since
tree-ssa is coming into mainline, I don't see much point in pursuing
my patch.

I didn't fully investigate why the tree-ssa code wasn't quite as good,
but basically it was because the register allocation wasn't quite as
good, and it required an extra shuffle.

Ian