Help with constraint for single register

Daniel Jacobowitz drow@false.org
Mon Dec 27 21:14:00 GMT 2004


On Mon, Dec 27, 2004 at 11:03:48AM -0500, Robert Baruch wrote:
> The strange thing is that apparently CSE has recognized this as an
> *addqi3 template, which doesn't make sense because this is that
> template:
> 
> (define_insn "*addqi3"
> 	[(set (match_operand:QI 0 "register_operand" "=r,W,W")
> 		  (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0")
>                    (match_operand:QI 2 "nonmemory_operand" "W,r,i")))]
>   ""
>   "\taddf %0,%2"
>   [(set_attr "cc" "all")]
>   )
> 
> Where "W" means the W register. There is no way that *addqi3 could
> match the insn.
> 
> QUESTION #1: Why is the CSE pass putting {*addqi3} in the insn?

It matches just fine, but requires reloads.  Constraints are for the
register allocator; predicates and insn conditions are for "matching".

As a general rule you want the insn condition and operand predicates to
accept only things which will satisfy an alternative in the
constraints.  This isn't a hard-and-fast rule because reload will take
care of you, but you get better code that way.

> QUESTION #2: How do I force the CSE pass, or any future pass to obey
> my restriction that all adds must take place through the W register?

You probably want an insn condition which asserts that either operand 1
or operand 2 is the W register.

-- 
Daniel Jacobowitz



More information about the Gcc mailing list