inadequate multiply-by-const expansion for pentium4

[Geert Bosch]

On Apr 28, 2004, at 06:40, Luchezar Belev wrote:
> I think that a group of instructions with lower total latency always 
> have
> better chance for good scheduling than single instruction with higher 
> latency
> because you always can just put them together in the place of the 
> single insn,
> but you can also shuffle them with the other instructions and further 
> hide latencies.

As Jim indicates, benchmarking non-trivial programs is the only
reasonable way to argue for changes that supposedly result in faster
code. You should use two compilers that are identical except for the
patch implementing your cost adjustments, and show SPEC results, as
well as code-size differences and compile times for each.

If your changes are not specific to a single target, you should
run these tests on a few non-similar architectures, such as PPC,
x86 and IA64.

This may seem like an overly large burden, but experience shows
that even though some optimization should in theory result in
faster code, secondary effects may make the net gain negligible
or even cause slow down, larger code or slower compile-times
without any apparent benefit.

If you are not able to do the testing yourself, you may choose
to prepare a patch and make some small test cases that show
significant improvement on a certain architecture. Then maybe
others with a suitable setup may be interested in helping with
the benchmarking.

   -Geert