sign/zero extension patterns

[Nathan Sidwell]

Hi,
in porting gcc to a new target, I have both signed and unsigned byte loads,
which obviously allow sign/zero extension to be done during a load. To
enable this, I have the following expands and insns defined,

(define_expand "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "")
	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
   ""
   "")

(define_insn "*sign_extend_qi_load"
   [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
   ""
   "load signed byte %0,%1")
This works fine, but I also need a define_insn for when the input
is not a memory_operand.  Here is what I've needed to get things
to not crash

(define_insn_and_split "*sign_extend_qi_reg"
   [(set (match_operand:SI 0 "register_operand" "=b")
	(sign_extend:SI (match_operand:QI 1 "register_operand" "b")))]
   ""
   "shift left %0,%1,24 ; shift right signed %0,%0,24"
   ""
   [(set (match_dup 2) (ashift:SI (match_dup 1) (const_int 24)))
    (set (match_dup 0) (ashiftrt:SI (match_dup 2) (const_int 24)))]
{
   operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
   if (GET_CODE (operands[1]) == SUBREG)
     operands[1] = XEXP (operands[1], 0);
   if (GET_MODE (operands[1]) != SImode)
     operands[1] = gen_rtx_SUBREG (SImode, operands[1], 0);
})

This seems a little clunky, what with all the SUBREG faffing about.
Is this correct, or is it just fragile?

nathan

-- 
Nathan Sidwell    ::   http://www.codesourcery.com   ::     CodeSourcery LLC
nathan@codesourcery.com    ::     http://www.planetfall.pwp.blueyonder.co.uk