G5 fpu optimizations for g77 3.4???

[Jack Howarth]

    I was wondering if anyone knew the exact state of fpu scheduling
optimizations in g77 of the current gcc 3.4 tree? I ask because 
the current gcc 3.1 compiled g77 code shows marginal performance on
a dual G5. My understanding is that the G5 is the first desktop
ppc with two fpu's per processor and will require specific fpu
scheduling changes to be implemented. Is this really the case and
what flags are operational in current gcc 3.4 g77 to do this?
Thanks in advance for any advice.
                         Jack
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Jack W. Howarth, Ph.D.                                    231 Albert Sabin Way
NMR Facility Director                              Cincinnati, Ohio 45267-0524
Dept. of Molecular Genetics                              phone: (513) 558-4420
Univ. of Cincinnati College of Medicine                    fax: (513) 558-8474