Unaligned half-word load (ARM)

[Richard Earnshaw]

> GCC is generating an odd instruction sequence that's causing me a bus
> fault. perhaps somebody here can expalain it to me.
> 	uint16_t* p = (a 32 bit aligned address);
> 	uint16_t foo = *p;
> GCC generates
> 	ldr	r1, [r5, #2]	@ load-rotate
> 	mov	r1, r1, lsr #16
> where r5 has the 32 bit aligned address. This causes a bus-fault since
> r5+2 is on a 16 bit boundary (but not 32), and attempts a 32-bit load
> from a 16-bit boundary. What's gone wrong?
> 
> arm-wince-pe-gcc (GCC) 3.2
> My target is an ARMSA1110 (Compaq iPAQ Pocket PC).
> 

Nothing.  This is the way early ARM processors fetched half-word data from 
memory.  If your memory system is configured to abort this case, then you 
need to compile either with -mcpu=strongarm1110 or with 
-malignment-faults.  The former is preferred if you are only targeting an 
iPAQ.

R.