USE insn and new register allocator

[Herman ten Brugge]

Hello,

I found a problem on the c4x target with the new register allocator.
I do not know if the problem is in the new register allocator or
if this is a problem on the c4x target.
The c4x target has defined the following define_epand:

(define_expand "ashlhi3_reg" 
 [(use (match_operand:HI 1 "reg_operand" ""))
  (use (match_operand:HI 0 "reg_operand" ""))
  /* If the shift count is greater than 32 this will give zero.  */
  (parallel [(set (match_dup 7)
                  (ashift:QI (match_dup 3)
                             (match_operand:QI 2 "reg_operand" "")))
             (clobber (reg:CC 21))])
  /* If the shift count is greater than 32 this will give zero.  */
  (parallel [(set (match_dup 8)
                  (ashift:QI (match_dup 4) (match_dup 2)))
             (clobber (reg:CC 21))])
  (parallel [(set (match_dup 10)
                  (plus:QI (match_dup 2) (const_int -32)))
             (clobber (reg:CC_NOOV 21))])
  /* If the shift count is greater than 32 this will do a left shift.  */
  (parallel [(set (match_dup 9)
                  (lshiftrt:QI (match_dup 3) (neg:QI (match_dup 10))))
             (clobber (reg:CC 21))])
  (set (match_dup 5) (match_dup 7))
  (parallel [(set (match_dup 6)
                  (ior:QI (match_dup 8) (match_dup 9)))
             (clobber (reg:CC 21))])]
 ""
 "
  operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
  operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
  operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
  operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
  operands[7] = gen_reg_rtx (QImode); /* lo << count */
  operands[8] = gen_reg_rtx (QImode); /* hi << count */
  operands[9] = gen_reg_rtx (QImode); /* lo >> (32 - count) */
  operands[10] = gen_reg_rtx (QImode); /* 32 - count */
 ")

The only inportend part is the two USE insns at the top. The new
register allocator emits these insns in the code. The old allocator
does not. This causes testcases to fail for the new register allocator.

These two insns are just there to allow us to generate the rest of
this define_expand.

Questions:
1) Is this the correct way to implement this in the md file. Should we
   modify the md file?

2) Should we change genemit.c to remove these USE insns? For example:

--- genemit.c	2003-05-11 14:32:19.000000000 +0200
+++ genemit.c.new	2003-05-11 14:33:46.000000000 +0200
@@ -524,6 +524,7 @@ gen_expand (expand)
   for (i = 0; i < XVECLEN (expand, 1); i++)
     {
       rtx next = XVECEXP (expand, 1, i);
+      if (GET_CODE (next) == USE) continue;
       if ((GET_CODE (next) == SET && GET_CODE (SET_DEST (next)) == PC)
 	  || (GET_CODE (next) == PARALLEL
 	      && ((GET_CODE (XVECEXP (next, 0, 0)) == SET
@@ -638,6 +639,7 @@ gen_split (split)
   for (i = 0; i < XVECLEN (split, 2); i++)
     {
       rtx next = XVECEXP (split, 2, i);
+      if (GET_CODE (next) == USE) continue;
       if ((GET_CODE (next) == SET && GET_CODE (SET_DEST (next)) == PC)
 	  || (GET_CODE (next) == PARALLEL
 	      && GET_CODE (XVECEXP (next, 0, 0)) == SET

   (This is what I use at the moment. And this fixes my problems.)

3) Shoud the new register allocation pass be changed to discard these
   USE insns?

4) Other solution?

Can some one help me with this?

	Herman.