Why does sparc build for you? or, why are make check results reported when it hasn't bootstrapped since May 5?

[Eric Botcazou]

> > This is the faulty patch:
> >
> > 2003-04-16  J"orn Rennecke <joern.rennecke@superh.com>
> >
> >         Re-apply this patch:
> >
> >         2002-05-16  Dale Johannesen  <dalej@apple.com>
> >           * combine.c (cant_combine_insn_p):  Reenable combinations
> >           involving hard regs unless CLASS_LIKELY_SPILLED_P.
>
> What makes you think this patch is faulty?

It seems that the combiner aggressively optimizes the code without taking 
into account or updating the liveness informations (see attached files). The 
problem was first reported on 04/17 by Kaveh so it wasn't difficult to 
pinpoint your patch. Reverting it fixes the bootstrap failure.

> It's a fairly straightforward patch.  it was originally pulled because
> of an x86 Ada bootstrap failure, but this patch is quite important for
> processors that pass arguments in registers to get good code, and further
> investigation of the Ada failure showed that it was due to a bug in a
> splitter in i386.md , which was easily fixed.

It may have uncovered a bug elsewhere then.

-- 
Eric Botcazou
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;; Function static jint java::lang::Float::floatToRawIntBits(__java_float)

112 registers.

Register 108 used 2 times across 2 insns in block 0; set 1 time; user var; 4 bytes.

Register 109 used 2 times across 2 insns in block 0; set 1 time; user var; 4 bytes.

Register 111 used 2 times across 2 insns in block 0; set 1 time.

1 basic blocks, 2 edges.

Basic block 0: first insn 31, last 30, prev -1, next -2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors:  ENTRY [100.0%]  (fallthru)
Successors:  EXIT [100.0%]  (fallthru)
Registers live at start: 14 [%sp] 23 [%l7] 31 [%i7] 33 [%f1] 101 [%sfp]
Registers live at end: 14 [%sp] 23 [%l7] 24 [%i0] 31 [%i7] 101 [%sfp]



try_optimize_cfg iteration 1

(note 1 0 31 ("<internal>") 5062)

;; Start of basic block 0, registers live: 14 [%sp] 23 [%l7] 31 [%i7] 33 [%f1] 101 [%sfp]
(note 31 1 3 0 [bb 0] NOTE_INSN_BASIC_BLOCK)

(insn 3 31 4 0 (nil) (set (reg/v:SF 108 [ value ])
        (reg:SF 33 %f1 [ value ])) 85 {*movsf_insn_novis} (nil)
    (expr_list:REG_DEAD (reg:SF 33 %f1 [ value ])
        (expr_list:REG_EQUIV (mem/f:SF (plus:DI (reg/f:DI 101 %sfp)
                    (const_int 128 [0x80])) [2 value+0 S4 A32])
            (nil))))

(note 4 3 10 0 NOTE_INSN_FUNCTION_BEG)

(note 10 4 11 0 ("<internal>") 5063)

(note 11 10 14 0 ("<internal>") 5064)

(insn 14 11 15 0 0x40731380 (set (subreg:SF (reg/v:SI 109 [ u ]) 0)
        (reg/v:SF 108 [ value ])) 85 {*movsf_insn_novis} (insn_list 3 (nil))
    (expr_list:REG_DEAD (reg/v:SF 108 [ value ])
        (nil)))

(note 15 14 18 0 ("<internal>") 5065)

(insn 18 15 24 0 0x40731380 (set (reg:DI 111 [ u ])
        (sign_extend:DI (reg/v:SI 109 [ u ]))) 148 {*sign_extendsidi2_insn} (insn_list 14 (nil))
    (expr_list:REG_DEAD (reg/v:SI 109 [ u ])
        (nil)))

(note 24 18 25 0 NOTE_INSN_FUNCTION_END)

(note 25 24 27 0 ("<internal>") 5066)

(insn 27 25 30 0 0x40731400 (set (reg/i:DI 24 %i0 [ <result> ])
        (reg:DI 111 [ u ])) 62 {*movdi_insn_sp64_novis} (insn_list 18 (nil))
    (expr_list:REG_DEAD (reg:DI 111 [ u ])
        (nil)))

(insn 30 27 0 0 0x40731400 (use (reg/i:DI 24 %i0 [ <result> ])) -1 (insn_list 27 (nil))
    (nil))
;; End of basic block 0, registers live:
 14 [%sp] 23 [%l7] 24 [%i0] 31 [%i7] 101 [%sfp]

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;; Function static jint java::lang::Float::floatToRawIntBits(__java_float)

(note 1 0 31 ("<internal>") 5062)

;; Start of basic block 0, registers live: 14 [%sp] 23 [%l7] 31 [%i7] 33 [%f1] 101 [%sfp]
(note 31 1 3 0 [bb 0] NOTE_INSN_BASIC_BLOCK)

(note 3 31 4 0 NOTE_INSN_DELETED)

(note 4 3 10 0 NOTE_INSN_FUNCTION_BEG)

(note 10 4 11 0 ("<internal>") 5063)

(note 11 10 14 0 ("<internal>") 5064)

(note 14 11 15 0 NOTE_INSN_DELETED)

(note 15 14 18 0 ("<internal>") 5065)

(note 18 15 24 0 NOTE_INSN_DELETED)

(note 24 18 25 0 NOTE_INSN_FUNCTION_END)

(note 25 24 27 0 ("<internal>") 5066)

(insn 27 25 30 0 0x40731400 (set (reg/i:DI 24 %i0 [ <result> ])
        (sign_extend:DI (subreg:SI (reg:DI 32 %f0 [orig:33 value+4 ] [33]) 4))) 148 {*sign_extendsidi2_insn} (nil)
    (expr_list:REG_DEAD (reg:SF 33 %f1 [ value ])
        (nil)))

(insn 30 27 0 0 0x40731400 (use (reg/i:DI 24 %i0 [ <result> ])) -1 (insn_list 27 (nil))
    (nil))
;; End of basic block 0, registers live:
 14 [%sp] 23 [%l7] 24 [%i0] 31 [%i7] 101 [%sfp]