ideas for modeling pipeline with bypass registers?

[tm_gccmail@mail.kloo.net]

On 28 Jul 2003, Greg McGary wrote:

> I'm working on a GCC port to a pipelined machine that has 1 insn
> latency between ALU operation and numbered-register writeback
> (i.e.,  insn-0: ALU op
>         insn-1: ...
>         insn-2: ALU op result appears in destination register
> 
> In order to make ALU ops available with no latency, there's a special
> "bypass" register that can be used before the register-file writeback.
> This bypass value is available for only one cycle, after which it is
> clobbered by the next ALU op.
> 
> Questions:
> 
> Are there any other GCC ports to CPUs with a similar architectural
> feature?

I just thought of this, but in a way this is similar to the original MIPS
without pipeline interlocks.

On the original MIPS implementations, the instructions had a fixed latency
and the pipeline would never stall. So if you tried to fetch a result
before it was ready, the register would be garbage.

If I understand correctly, this is handled at the assembler level by
having the assembler emit NOPs if the compiler emits code where the
latency requirements are not met.

This is turned on/off with the ".set reorder" and ".set
noreorder" assembler directives.

Toshi