ideas for modeling pipeline with bypass registers?

[tm_gccmail@mail.kloo.net]

On 28 Jul 2003, Greg McGary wrote:

> I'm working on a GCC port to a pipelined machine that has 1 insn
> latency between ALU operation and numbered-register writeback
> (i.e.,  insn-0: ALU op
>         insn-1: ...
>         insn-2: ALU op result appears in destination register
> 
> In order to make ALU ops available with no latency, there's a special
> "bypass" register that can be used before the register-file writeback.
> This bypass value is available for only one cycle, after which it is
> clobbered by the next ALU op.

I'm assuming this bypass register is an architecturally visible register?

Toshi