Transformations to increase parallelism

[Dorit Naishlos]

> No. I've mentioned similar problems before on this list, though.
>
> GCC really needs a pass to preprocess the instructions before sched1 to
> give the scheduler more scheduling freedom, especially on many-issue
> processors.

Yes, this is true for our port too (power4). going back to the problem
you raised a couple of weeks ago ("Pre_dec and Post_inc insns" -
http://gcc.gnu.org/ml/gcc/2003-07/msg00021.html) :

> > IMHO, the pre/post increment/decrement addressing modes should be
> > generated after sched1 to give the first scheduling pass maximum
freedom
> > for reordering instructions.
>
> IMHO whether to have autoincdec at sched1 should be
> target-dependent, supposedly through an option like others set
> by a target at OPTIMIZE_OPTIONS, after careful measurements.

Pre/post increment/decrement addressing modes contain additional
dependences between insns thereby restricting scheduler freedom of action,
as pointed out. For our target (power4) such modes are also more expensive
in terms of resource consumption, so it may be beneficial to decide on
using
these modes after sched1, be it controlled by a target dependent flag or
not.

Other compiler stages may be able to generate better code w/o these address
forms (we encountered such a situation when trying to optimize addressing
during combine); in fact, it may even be beneficial if this decision would
take place as late as possible (possibly even after sched2...?).

Dorit