Implementing fine grain parallelism and automatic support for SIMD ISA extensions in gcc

[Martin Brain]

Hi,
   I'm currently working for Bath University Computing Scienece
department and we are interested in investigating fine grain parallelism
in compiliation.  As far as I know no free compiler supports automatic
synthesis of vector instructions, although icc does have support for
this style of thing for P3 and P4 chips.  I would be trying to make this
code as architecture independant as possible but aiming towards support
for AltiVec, VIS, 3DNow and SSE first.
  Do people feel it is viable and worthwhile to attempt this?  Is anyone
else working on this / thinking of doing so at the moment?  Would it be
possible to integrate this with the existing support of vector data
types?  Thanks for your thoughts.

Cheers,
 - Martin