Pre_dec and Post_inc insns

[Hans-Peter Nilsson]

On Wed, 9 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> The load latency usually is two, BTW. This is fairly typical for a
> pipelined processor with 5 stages. The Pentium, the SH, many MIPS and
> other processors have a load latency of two clocks.

But one I'm working on only has a one cycle load latency...

Nevertheless, I hope you get my point that the usefulness of
generating autoincdec before sched1 is a highly target-dependent
detail, and that forcing one way or the other by making
assumptions on universal latency figures would be bad.

brgds, H-P