Pre_dec and Post_inc insns

[tm_gccmail@mail.kloo.net]

On Mon, 30 Jun 2003, Natasha Wilson wrote:

> Hi,
> 
> According to the GCC manual for embedded side effects, :
> 
>   These embedded side effect expressions must be used with 
>   care. Instruction patterns may not use them. Until the
>   flow pass of the compiler, they may occur only to
>   represent pushes onto the stack. The flow pass finds
>   cases where registers are incremented or decremented in
>   one instruction and used as an address shortly before or
>   after; these cases are then transformed to use pre-
>   or post-increment or -decrement. 
> 
> The manual says that such insns are ambiguous or disallowed. Why is that so?
> 
> What are the potentials areas where they could create problems if they are generated before the flow pass?
> 
> As most architectures provide post_inc and pre_dec facilities, couldn't we generate better code if this were allowed and we generated such insns during the RTL generation phase itself?
> 
> Regards,
> 
> Natasha

IMHO, the pre/post dec/inc shouldn't be generated before sched1 because
these cause major problems with instruction scheduling.

Consider a processor with a memory load latency of two clocks:

	mov.l	@r4+,r1
	mov.l	@r4+,r2
	mov.l	@r4+,r3
	add	r2,r3

sched1 will be unable to reorder this sequence to:

	add	#4,r4
	mov.l	@r4+,r2
	mov.l	@r4,r3
	add	#-8,r4
	mov.l	@r4,r1
	add	r2,r3

because of the post-increment addressing.

IMHO, the pre/post increment/decrement addressing modes should be
generated after sched1 to give the first scheduling pass maximum freedom
for reordering instructions.

Toshi