[3.3 branch] IA64 bootstrap failure

[Andreas Schwab]

Eric Botcazou <ebotcazou@libertysurf.fr> writes:

|> > @@ -2054,10 +2054,10 @@
|> >      2a50:	0b 70 00 1e 18 10 	[MMI]       ld8 r14=[r15];;
|> >      2a56:	70 00 38 0c 72 00 	            cmp.eq p7,p6=0,r14
|> >      2a5c:	00 00 04 00       	            nop.i 0x0;;
|> > -    2a60:	dc 00 20 40 98 11 	[MFB] (p06) st8 [r32]=r8
|> > +    2a60:	fc 00 20 1e 98 11 	[MFB] (p07) st8 [r15]=r8
|> >      2a66:	00 00 00 02 00 00 	            nop.f 0x0
|> >      2a6c:	00 00 00 20       	            nop.b 0x0
|> > -    2a70:	e0 00 20 1e 98 11 	[MII] (p07) st8 [r15]=r8
|> > +    2a70:	c0 00 20 40 98 11 	[MII] (p06) st8 [r32]=r8
|> >      2a76:	f0 c0 22 00 42 00 	            adds r15=88,r8
|> >      2a7c:	04 40 00 84       	            mov r32=r8
|> >      2a80:	0a 70 00 46 18 10 	[MMI]       ld8 r14=[r35];;
|> 
|> It bears some ressemblance with PR optimization/11320, where the machine 
|> dependent reorg pass also swaps two insns.

Could be, but then I would have expected that the stage1 compiler
generates the same code.  I'd rather think this is similar to the problem
that lead to the replacement of PWD with PWD_COMMAND.

Andreas.

-- 
Andreas Schwab, SuSE Labs, schwab@suse.de
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