PR #5753
Peter Barada
pbarada@mail.wm.sps.mot.com
Tue Mar 5 12:45:00 GMT 2002
>I've reported a PR (see #5753) while compiling some code from a
>m68k-elf configured 3.0.4 compiler for -m5200. I'm attempting to
>figure out a fix.
Since QImode can not be placed in address registers, I've tried
modifying HARD_REGNO_MODE_OK() to be:
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((TARGET_5200 && ((REGNO) >= 8 && (REGNO) < 16) \
&& GET_MODE_SIZE (MODE) == 1) ? 0 : \
(((REGNO) < 16 \
&& !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
|| ((REGNO) >= 16 && (REGNO) < 24 \
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
&& GET_MODE_UNIT_SIZE (MODE) <= 12)))
and this caused the compilation to break with:
/tmp/crap-304-new/bin/m68k-elf-gcc -c -gstabs -malign-int -m5200 /tmp/cfprintf4.c -o /tmp/cfprintf4.o
/tmp/cfprintf4.c: In function `_vformat':
/tmp/cfprintf4.c:58: Unable to find a register to spill in class `ADDR_REGS'.
/tmp/cfprintf4.c:58: This is the insn:
(insn 185 184 186 (set (reg:SI 68)
(plus:SI (subreg:SI (mem/f:QI (plus:SI (reg/f:SI 14 %a6)
(const_int -1 [0xffffffff])) 0) 0)
(const_int -100 [0xffffff9c]))) 100 {*addsi3_5200} (nil)
(nil))
/tmp/cfprintf4.c:58: confused by earlier errors, bailing out
So to go the next step, I modified LIMIT_RELOAD_CLASS() to evaluate to
DATA_REGS if CLASS is ADDR_REGS and mode is QImode, and this caused
the compilation ot break with:
/tmp/cfprintf4.c:58: Insn does not satisfy its constraints:
(insn 185 258 256 (set (reg:SI 8 %a0)
(plus:SI (reg:SI 0 %d0)
(const_int -100 [0xffffff9c]))) 100 {*addsi3_5200} (nil)
(nil))
So I can see how the reload code replaced the previous subreg with
%d0, and why it doesn't match... I guess the real question I have to
figure out is why is class ADDR_REGS in the first place...
1) Are my changes to these three macros the right changes?
2) Am I on the right track?
--
Peter Barada Peter.Barada@motorola.com
Wizard 781-852-2768 (direct)
WaveMark Solutions(wholly owned by Motorola) 781-270-0193 (fax)
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