DFA Instruction Output for VLIW

[Vladimir Makarov]

law@redhat.com wrote:
> 
> In message <3D0A266A.8B4932FB@picochip.com>, Dan Towner writes:
>  > Hi all,
>  >
>  > I am using the DFA to schedule code for a VLIW. The assembly language
>  > for the target has VLIW packets of the form:
>  >
>  > insn1 | insn2 | insn3
>  >
>  > At the moment, I can only get the scheduler to emit VLIW'd instructions
>  > on successive lines. What is the easiest way to get the DFA scheduler to
>  > generate instructions in a single line format, or alternatively,
>  > generate a continuation on the end of each VLIW'ed line, but stopping
>  > once it has reached the end of the VLIW packet:
>  >
>  > insn1 \
>  > insn2 \
>  > insn3
>  >
>  > Furthermore, some common instructions such as add's or copy's have to
>  > mark the EU to which they should be issued:
>  >
>  > ADD.0 something | ADD.1 somethingElse
>  >
>  > I think that I can solve this by using TARGET_SCHED_REORDER to set an
>  > attribute for the instruction, marking the EU to which it should be
>  > issued. Does this seem feasible?
> The scheduler doesn't handle this kind of stuff.  It can note which insns
> are in a VLIW group, but it is not responsible for the actual output
> of instructions.
> 
> Basically the scheduler will mark the leader or the end of each VLIW
> group (I don't recall which offhand).  You're going to need to tweak
> your backend to use that information to get the output you want.

  Jeff is right.  This is not DFA scheduler's responsibility.  The
scheduler does mark insns starting new cycle by TImode on the 2nd insn
scheduling.  But you should not use this information because there are
some optimizations (e.g. jump optimization) after the 2nd insn
scheduling which could make the marks obsolete.

  You could use the marks if the insn scheduling after reload is the
last optimization in compiler.  IA64 port is an example how to make the
2nd insn scheduling the last optimization.  But IA64 port does not use
DFA scheduler yet.

  You could use dfa pipeline hazard recognizer on final phase (see macro
FINAL_PRESCAN_INSN) to find start of a new VLIW insn and get an
execution unit used by the insn.  In this case you should describe such
units as (define_query_cpu_unit).

Vlad