The perennial i386 floating-point rounding issue...

[Jan Hubicka]

> >-march isn't a reliable guide to whether SSE is available, at least for
> >AMD chips. According to AMD's docs, everything from the Athlon 4
> >(a.k.a. Thunderbird) on has been made in both SSE and no-SSE versions,
> >and the only reliable way to detect SSE is via the feature flags from
> >the CPUID instruction.
> 
> Sorry, this just isn't true.  No Thunderbirds (aka Athlon model 4) were ever
> made with SSE support.

Thats it.  THere is little bug in SPECs making GCC to define __SSE__ for
tbirds.  I believe it is fixed already, I will double check.
> 
> Perhaps you are confusing the "Mobile AMD Athlon??? 4" which is the name of their
> mobile processor based on the Palomino core aka (Athlon model 6).  All the
> processors based on this core (or the newest model 8 core) are SSE capable.

More sick is that the SSE needs to be enabled in bios and some of the
mobille biosses don't, so you effectivly get core without SSE support,
but this is the case of compilation under non-SSE-capable OS and I guess
we can require users to manually specify -mno-sse in such cases.
THis has been primary motivation for keeping the -msse switches around.
> 
> The same distinction holds for the Duron line.  All model 3s are not SSE
> capable.  All model 7s are.  However like Celeron's, Duron's aren't listed as
> seperate processors for GCC tuning.

Yes, AMD and Intel marketing is making our life interesting.

Honza
> 
> Kelley Cook